
`timescale 1ns / 1ns




module tb_WR_interface();



reg i_clk, i_rst;
wire WRflag, WR_finish;
reg wr_trig;
reg [7:0] WR_addr, WR_data;




wire chip_oeWR;
wire [7:0] sja1000_data_wrWR;
wire sja1000_wr_nWR;
wire sja1000_aleWR;
wire sja1000_cs_nWR;






WR_interface WR_interface_inst(
. i_clk(i_clk),
. i_rst(i_rst), 
. o_WRflag(WRflag), 
. wr_trig(wr_trig),
. WR_addr(WR_addr),
. WR_data(WR_data),
. o_WR_finish(WR_finish), 
. o_chip_oe(chip_oeWR), 
. o_sja1000_data_wr(sja1000_data_wrWR), 
. o_sja1000_wr_n(sja1000_wr_nWR), 
. o_sja1000_ale(sja1000_aleWR),
. o_sja1000_cs_n(sja1000_cs_nWR));





 initial begin
    i_clk = 1'b0;
	i_rst = 1'b1;
    #20
    i_rst = 1'b0;
	
	
	
    #1
    wr_trig = 1'b1;
	WR_addr = 8'h1F;
	WR_data = 8'hC8;
    #2
	wr_trig = 1'b0;
	WR_addr = 8'h0;
	WR_data = 8'h0;
	
	
    #100
    wr_trig = 1'b1;
	WR_addr = 8'h2E;
	WR_data = 8'hB7;
    #2
	wr_trig = 1'b0;
	WR_addr = 8'h0;
	WR_data = 8'h0;
	
	
	#100
    wr_trig = 1'b1;
	WR_addr = 8'h3D;
	WR_data = 8'hC6;
    #2
	wr_trig = 1'b0;
	WR_addr = 8'h0;
	WR_data = 8'h0;

	
 end
 
 
   
always#1 i_clk = ~i_clk;

   
   
endmodule

